The power management system for the conventional processor (such as the processors inside smart phones or cars) usually has a set of low dropout (LDO) regulators to dynamically adjust voltages. Generally, the LDO regulator is primarily embodied by the analog control technology or the sync digital control technology.
If the LDO regulator is embodied by the analog control technology, the reaction speed of the LDO regulator actively adjusting the voltage is limited by the bandwidth related with the analog control circuit, so the speed of adjusting the voltage cannot be increased effectively. Furthermore, when the LDP regulator operates in the static state, since the LDO regulator still needs to provide the bias current to maintain its operation, the static work current for the analog control circuit cannot be decreased during the static state.
If the LDO regulator is embodied by the sync digital control technology, the reaction speed of the LDO regulator dynamically adjusting the voltage is limited by the clock rate of the clock frequency signal for the digital control circuit. In order to increase the reaction speed of the LDO regulator actively adjusting the voltage, the clock rate of the clock frequency signal has to be increased. However, increasing the clock rate of the clock frequency signal will increase the current waste of the digital control circuit and also cause the occurrence of inrush current.